This invention relates to semiconductor memory devices, and more particularly to an improved static MOS RAM.
In the semiconductor memory devices used in small minicomputers and microprocessor systems, static memory has an advantage compared to dynamic memory in that static does not require refresh. Dynamic MOS RAMs employ one-transistor cells compared to six transistor cells in static RAMs, so the dynamic devices are much lower in cost because higher densities are achieved on smaller bar sizes. Unfortunately, the storage capacitors in dynamic cells leak charge and the data must be periodically refreshed by addressing each row of a memory array. In large memory systems, the circuitry required for refresh is small in proportion, but in the small memory associated with microcomputers or small minicomputers the refresh control circuitry is a significant portion of the system cost, so static RAMs must be used. Previous attempts to reduce the cell size in static or pseudo static RAMs to make them more comp table with dynamic RAMs include the following patents or applications, all assigned to Texas Instruments:
U.S. Pat. No. 3,995,181 issued to Joseph H. Raymond, Jr. PA1 Ser. No. 671,252, filed May 28, 1976 by G. R. Mohan Rao, now U.S. Pat. No. D246,679. PA1 Ser. No. 727,116, filed Sept. 27, 1976 by Rao et. al. now U.S. Pat. No. 4,110,776. PA1 Ser. No. 762,916, filed Jan. 27, 1977 by David J. McElroy, now U.S. Pat. No. 4,142,111.
It is a principal object of this invention to provide improved memory devices made in a semiconductor integrated circuits. Another object is to provide an improved "static" type MOS memory device, particularly a memory device of small cell size. An additional object is to provide a method of making small area pseudo static memory elements in semiconductor integrated circuits.